This section is intended to provide information relevant to understanding various technologies described herein. As the section's title implies, this is a discussion of related art that should in no way imply that it is prior art. Generally, related art may or may not be considered prior art. It should therefore be understood that any statement in this section should be read in this light, and not as any admission of prior art.
In modern circuit design, scan cell chains and related mechanisms are used for testing an integrated circuit (IC) by providing a means for observing flip-flop output. In full scan design, automatic test pattern generation (ATPG) provides for simpler application of combinatorial testing. In some current memory macro designs, embedded scan chains may not be present on address pins and control pins.
For ATPG coverage on these pins, there are some techniques that may be used on a system-on-chip (SoC) level. One example technique may generate random access memory (RAM) based sequential ATPG patterns. This technique may have a downside in run time for an ATPG tool to generate patterns as well as an increase in ATPG pattern count, which may result in increased test time and testing cost. Another technique may add observation scan cells on drivers of input pins of the memory macro. Unfortunately, this technique may result in additional hardware cost on the SoC level.